Protocol Forge: Visual Protocol Designer with Open Hardware Emulation

Protocol Forge is a desktop application that bridges the gap between protocol design and embedded implementation. It provides an interactive canvas where engineers can visually define custom communication protocols - from the physical layer (timing diagrams, signal waveforms) up to the application layer (packet structures, state machines). The tool then automatically generates synthesizable Verilog or VHDL code for FPGA-based hardware emulation, as well as driver code in C or Rust for microcontrollers. A key innovation is its tight integration with open-source FPGA toolchains (Yosys, nextpnr) and simulation backends (Verilator), allowing developers to test their protocol designs in software before committing to hardware. The entire project, including the reference open FPGA board design (based on the Lattice iCE40 family), is released under open-source licenses, encouraging community contributions and customization.

Embedded developers working with custom or proprietary communication protocols face a painful iterative cycle: they manually write bit-banging code, connect a logic analyzer or oscilloscope, and tweak timing by guesswork. There is no unified tool that lets them design a protocol visually, simulate it accurately, and generate both hardware and software implementations from a single model. Existing solutions are either too low-level (waveform editors) or too high-level (protocol analyzers), leaving a gap in the workflow. Protocol Forge aims to fill that gap by providing an opinionated, end-to-end design environment that treats protocols as first-class, reusable artifacts.

• Provide a drag-and-drop visual editor for defining protocol layers (timing diagrams, state machines, packet structures)
• Generate synthesizable Verilog/VHDL for FPGA-based hardware emulation (open toolchain)
• Generate microcontroller-friendly driver code in C and Rust
• Include a software emulator (Verilator) that runs protocol tests on the developer's machine
• Open-source all hardware designs (reference FPGA board) and tool software
• Ship with a library of standard protocol templates (I2C, SPI, UART, CAN) and easy customization

• Not a full IDE for embedded development (no editor for general firmware)
• Not a production-grade synthesis tool (focus on rapid prototyping and early validation)
• Not intended for complex network protocols like TCP/IP or HTTP (target is low-level bus protocols)
• Not a replacement for logic analyzers or oscilloscopes in final debugging
• Not a commercial product; solely open-source community project

Desktop App: Electron + React with interactive waveform rendering using D3.js and custom Canvas layers. Code Generation: Node.js backend with Handlebars templates for Verilog, VHDL, C, and Rust. Simulation: Verilator (open-source Verilog simulator) integrated via child process, with real-time waveform output. Hardware: Open reference FPGA board based on Lattice iCE40 (e.g., IceBreaker), with fully open schematic and PCB layout (KiCad). Toolchain: Yosys for synthesis, nextpnr for place-and-route, and openFPGALoader for board programming. Storage: Project files are JSON-based, easily diffable and version-controlled with Git.

The tool is structured as a monolith desktop application with a clear separation between frontend and backend logic. The Core Model is a JSON schema that describes protocols hierarchically: physical layer (timing parameters, signal definitions), data link layer (packet formats, fields, CRC), and state machines (transitions, actions). The Frontend provides a canvas where users visually compose protocols: drag timing waveforms onto a timeline, draw state machines as boxes and arrows, and define packet structures with nested fields. The Backend (running in Electron's main process) takes the model and generates code: it walks the model and emits Verilog modules with proper clock domain crossing, or C code with bit-banging loops. Simulation is triggered via a button, which spawns a Verilator process that compiles the generated Verilog into a simulation binary that communicates with the UI via UDP (or FIFO files) to stream waveform data back for real-time display. The open hardware board is designed to be a simple USB-stick with a small FPGA, USB-serial, and GPIO headers; the tool can program it directly via DFU or openFPGALoader.

1. Simulation complexity: Achieving cycle-accurate simulation for complex protocols (e.g., with dynamic clock stretching) may be extremely difficult and could limit the tool's reliability.
2. Niche adoption: The intersection of FPGA enthusiasts and embedded developers is small; building a vibrant open-source community will be challenging.
3. Toolchain fragility: Open FPGA toolchains evolve rapidly; keeping integration working across platforms (Windows, macOS, Linux) is a maintenance burden.
4. Generated code quality: Automatically generated hardware descriptions may be less efficient than handcrafted ones, potentially discouraging serious use.
5. Hardware availability: The chosen reference board may become obsolete or hard to source, requiring constant updates.

1. Should the simulation support multi-device scenarios (e.g., SPI with master and multiple slaves)?
2. How to handle analog aspects like signal rise/fall times or noise in simulation?
3. Which open-source board to target first: IceBreaker (iCE40) or OrangeCrab (ECP5)?
4. Should we use a proprietary waveform rendering engine (e.g., GtkWave's backend) for performance, or roll our own?
5. How to incentivize community contributions to the protocol template library?

The team had a working prototype of the protocol editor with basic waveform drawing and code generation for C, but integrating the FPGA simulation proved too time-consuming. The lead developer switched jobs, the target open-hardware board (IceBreaker) went out of stock for months, and the project simply lost momentum. It remains a solid concept that might return with renewed interest.

This project was conceived in early 2023 by a small group of embedded systems engineers at a hardware startup. The name 'Protocol Forge' was chosen to evoke the idea of shaping metal (hardware) with precision. The open-hardware angle was critical: they wanted to democratize protocol development, not just sell a tool.